/*******************************************************************************
 *
 * Copyright (c) 2004-2008 by Vivante Corp.  All rights reserved.
 *
 * The material in this file is confidential and contains trade secrets of
 * Vivante Corporation.  This is proprietary information owned by Vivante
 * Corporation.  No part of this work may be disclosed, reproduced, copied,
 * transmitted, or used in any way for any purpose, without the express
 * written permission of Vivante Corporation.
 *
 ******************************************************************************/

/*******************************************************************************
 *
 * This file is automatically generated on Mon Apr 13 01:22:32 2009
 *
 * Any changes made to this file are lost at the next compile run!
 * So better make sure you update the source .r files instead!
 *
 ******************************************************************************/

////////////////////////////////////////////////////////////////////////////////
//                               ~~~~~~~~~~~~~~                               //
//                               Module Resolve                               //
//                               ~~~~~~~~~~~~~~                               //
////////////////////////////////////////////////////////////////////////////////

// Register AQRsTrigger.
// ~~~~~~~~~~~~~~~~~~~~
#define AQRsTriggerRegAddrs                                               0x0580
#define AQ_RS_TRIGGER_Address                                            0x01600
#define AQ_RS_TRIGGER_MSB                                                     15
#define AQ_RS_TRIGGER_LSB                                                      0
#define AQ_RS_TRIGGER_Count                                                    1
#define AQ_RS_TRIGGER_FieldMask                                       0x00000001
#define AQ_RS_TRIGGER_ReadMask                                        0x00000001
#define AQ_RS_TRIGGER_WriteMask                                       0x00000001
#define AQ_RS_TRIGGER_ResetValue                                      0x00000000

// Trigger resolve operation after configuring other registers.
#define AQ_RS_TRIGGER_TRIG                                                   0:0
#define AQ_RS_TRIGGER_TRIG_End                                                 0
#define AQ_RS_TRIGGER_TRIG_Start                                               0

// Register AQRsConfig.
// ~~~~~~~~~~~~~~~~~~~
#define AQRsConfigRegAddrs                                                0x0581
#define AQ_RS_CONFIG_Address                                             0x01604
#define AQ_RS_CONFIG_MSB                                                      15
#define AQ_RS_CONFIG_LSB                                                       0
#define AQ_RS_CONFIG_Count                                                     1
#define AQ_RS_CONFIG_FieldMask                                        0x77775FFF
#define AQ_RS_CONFIG_ReadMask                                         0x77775FFF
#define AQ_RS_CONFIG_WriteMask                                        0x77775FFF
#define AQ_RS_CONFIG_ResetValue                                       0x00000000

// Source color format.
#define AQ_RS_CONFIG_RS_SRC_FORMAT                                           4:0
#define AQ_RS_CONFIG_RS_SRC_FORMAT_End                                         4
#define AQ_RS_CONFIG_RS_SRC_FORMAT_Start                                       0
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_X4R4G4B4                               0x00
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_A4R4G4B4                               0x01
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_X1R5G5B5                               0x02
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_A1R5G5B5                               0x03
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_R5G6B5                                 0x04
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_X8R8G8B8                               0x05
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_A8R8G8B8                               0x06
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_YUY2                                   0x07
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_UYVY                                   0x08
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_INDEX8                                 0x09
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_MONOCHROME                             0x0A
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_HDR7E3                                 0x0B
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_HDR6E4                                 0x0C
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_HDR5E5                                 0x0D
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_HDR6E5                                 0x0E
#define   AQ_RS_CONFIG_RS_SRC_FORMAT_YV12                                   0x0F

#define AQ_RS_CONFIG_RS_SRC_SUPER_SAMPLE                                     6:5
#define AQ_RS_CONFIG_RS_SRC_SUPER_SAMPLE_End                                   6
#define AQ_RS_CONFIG_RS_SRC_SUPER_SAMPLE_Start                                 5
#define   AQ_RS_CONFIG_RS_SRC_SUPER_SAMPLE_DISABLE                           0x0
#define   AQ_RS_CONFIG_RS_SRC_SUPER_SAMPLE_ENABLE2X1                         0x1
#define   AQ_RS_CONFIG_RS_SRC_SUPER_SAMPLE_ENABLE1X2                         0x2
// Supersampling mode.
#define   AQ_RS_CONFIG_RS_SRC_SUPER_SAMPLE_ENABLE2X2                         0x3

#define AQ_RS_CONFIG_RS_SRC_TILE_ENABLE                                      7:7
#define AQ_RS_CONFIG_RS_SRC_TILE_ENABLE_End                                    7
#define AQ_RS_CONFIG_RS_SRC_TILE_ENABLE_Start                                  7
#define   AQ_RS_CONFIG_RS_SRC_TILE_ENABLE_DISABLE                            0x0
// Shows if source is tiled or not (used in supersampling).
#define   AQ_RS_CONFIG_RS_SRC_TILE_ENABLE_ENABLE                             0x1

// Destination color format.
#define AQ_RS_CONFIG_RS_DEST_FORMAT                                         12:8
#define AQ_RS_CONFIG_RS_DEST_FORMAT_End                                       12
#define AQ_RS_CONFIG_RS_DEST_FORMAT_Start                                      8
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_X4R4G4B4                              0x00
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_A4R4G4B4                              0x01
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_X1R5G5B5                              0x02
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_A1R5G5B5                              0x03
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_R5G6B5                                0x04
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_X8R8G8B8                              0x05
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_A8R8G8B8                              0x06
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_YUY2                                  0x07
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_UYVY                                  0x08
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_INDEX8                                0x09
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_MONOCHROME                            0x0A
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_HDR7E3                                0x0B
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_HDR6E4                                0x0C
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_HDR5E5                                0x0D
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_HDR6E5                                0x0E
#define   AQ_RS_CONFIG_RS_DEST_FORMAT_YV12                                  0x0F

#define AQ_RS_CONFIG_RS_DEST_TILE_ENABLE                                   14:14
#define AQ_RS_CONFIG_RS_DEST_TILE_ENABLE_End                                  14
#define AQ_RS_CONFIG_RS_DEST_TILE_ENABLE_Start                                14
#define   AQ_RS_CONFIG_RS_DEST_TILE_ENABLE_DISABLE                           0x0
// Shows if destination is tiled or not (used in supersampling).
#define   AQ_RS_CONFIG_RS_DEST_TILE_ENABLE_ENABLE                            0x1

#define AQ_RS_CONFIG_RS_EDGE_DETECT_ENABLE                                 16:16
#define AQ_RS_CONFIG_RS_EDGE_DETECT_ENABLE_End                                16
#define AQ_RS_CONFIG_RS_EDGE_DETECT_ENABLE_Start                              16
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_ENABLE_DISABLE                         0x0
// Enables/disables edge detection based filtering.
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_ENABLE_ENABLE                          0x1

#define AQ_RS_CONFIG_RS_EDGE_DETECT_ZMETHOD                                17:17
#define AQ_RS_CONFIG_RS_EDGE_DETECT_ZMETHOD_End                               17
#define AQ_RS_CONFIG_RS_EDGE_DETECT_ZMETHOD_Start                             17
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_ZMETHOD_NONE                           0x0
// Edge detection method.
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_ZMETHOD_DIFF2                          0x1

// If it is on a line, don't filter the pixel.
#define AQ_RS_CONFIG_RS_EDGE_DETECT_LINE_CHECK                             18:18
#define AQ_RS_CONFIG_RS_EDGE_DETECT_LINE_CHECK_End                            18
#define AQ_RS_CONFIG_RS_EDGE_DETECT_LINE_CHECK_Start                          18
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_LINE_CHECK_DISABLE                     0x0
// If enabled, check if the pixel is on a line.
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_LINE_CHECK_ENABLE                      0x1

#define AQ_RS_CONFIG_RS_EDGE_DETECT_SMETHOD                                20:20
#define AQ_RS_CONFIG_RS_EDGE_DETECT_SMETHOD_End                               20
#define AQ_RS_CONFIG_RS_EDGE_DETECT_SMETHOD_Start                             20
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_SMETHOD_DISABLE                        0x0
// Using Stencil to detect the edge. Same stencil should be at same object.
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_SMETHOD_ENABLE                         0x1

#define AQ_RS_CONFIG_RS_EDGE_DETECT_CMETHOD                                21:21
#define AQ_RS_CONFIG_RS_EDGE_DETECT_CMETHOD_End                               21
#define AQ_RS_CONFIG_RS_EDGE_DETECT_CMETHOD_Start                             21
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_CMETHOD_DISABLE                        0x0
// Using subpixel color difference to detect an edge.
#define   AQ_RS_CONFIG_RS_EDGE_DETECT_CMETHOD_ENABLE                         0x1

// Depth format.
#define AQ_RS_CONFIG_DEPTH_FORMAT                                          22:22
#define AQ_RS_CONFIG_DEPTH_FORMAT_End                                         22
#define AQ_RS_CONFIG_DEPTH_FORMAT_Start                                       22
#define   AQ_RS_CONFIG_DEPTH_FORMAT_Z16                                      0x0
#define   AQ_RS_CONFIG_DEPTH_FORMAT_Z24                                      0x1

// Depth buffer interleaving.
#define AQ_RS_CONFIG_INTERLEAVED                                           26:24
#define AQ_RS_CONFIG_INTERLEAVED_End                                          26
#define AQ_RS_CONFIG_INTERLEAVED_Start                                        24
#define   AQ_RS_CONFIG_INTERLEAVED_DISABLED                                  0x0
#define   AQ_RS_CONFIG_INTERLEAVED_C16D16                                    0x1
#define   AQ_RS_CONFIG_INTERLEAVED_C16D32                                    0x2
#define   AQ_RS_CONFIG_INTERLEAVED_C32D16                                    0x3
#define   AQ_RS_CONFIG_INTERLEAVED_C32D32                                    0x4

#define AQ_RS_CONFIG_RS_SRC_DEPTH_TILE_ENABLE                              28:28
#define AQ_RS_CONFIG_RS_SRC_DEPTH_TILE_ENABLE_End                             28
#define AQ_RS_CONFIG_RS_SRC_DEPTH_TILE_ENABLE_Start                           28
#define   AQ_RS_CONFIG_RS_SRC_DEPTH_TILE_ENABLE_DISABLE                      0x0
// Shows if depth buffer is tiled or not (used in supersampling).
#define   AQ_RS_CONFIG_RS_SRC_DEPTH_TILE_ENABLE_ENABLE                       0x1

// display controller format requirements.
#define AQ_RS_CONFIG_FLIP_RB                                               29:29
#define AQ_RS_CONFIG_FLIP_RB_End                                              29
#define AQ_RS_CONFIG_FLIP_RB_Start                                            29
#define   AQ_RS_CONFIG_FLIP_RB_DISABLE                                       0x0
// Flips the red and blue color data to match different
#define   AQ_RS_CONFIG_FLIP_RB_ENABLE                                        0x1

#define AQ_RS_CONFIG_FLIP_Y                                                30:30
#define AQ_RS_CONFIG_FLIP_Y_End                                               30
#define AQ_RS_CONFIG_FLIP_Y_Start                                             30
#define   AQ_RS_CONFIG_FLIP_Y_DISABLE                                        0x0
// Flips Y, upside down of the graphic, OpenVG required
#define   AQ_RS_CONFIG_FLIP_Y_ENABLE                                         0x1

// Register AQRsSrcAddress.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Source color address.

#define AQRsSrcAddressRegAddrs                                            0x0582
#define AQ_RS_SRC_ADDRESS_Address                                        0x01608
#define AQ_RS_SRC_ADDRESS_MSB                                                 15
#define AQ_RS_SRC_ADDRESS_LSB                                                  0
#define AQ_RS_SRC_ADDRESS_Count                                                1
#define AQ_RS_SRC_ADDRESS_FieldMask                                   0xFFFFFFFF
#define AQ_RS_SRC_ADDRESS_ReadMask                                    0xFFFFFFFC
#define AQ_RS_SRC_ADDRESS_WriteMask                                   0xFFFFFFFC
#define AQ_RS_SRC_ADDRESS_ResetValue                                  0x00000000

#define AQ_RS_SRC_ADDRESS_TYPE                                             31:31
#define AQ_RS_SRC_ADDRESS_TYPE_End                                            31
#define AQ_RS_SRC_ADDRESS_TYPE_Start                                          31
#define   AQ_RS_SRC_ADDRESS_TYPE_SYSTEM                                      0x0
#define   AQ_RS_SRC_ADDRESS_TYPE_VIRTUAL_SYSTEM                              0x1

#define AQ_RS_SRC_ADDRESS_ADDRESS                                           30:0
#define AQ_RS_SRC_ADDRESS_ADDRESS_End                                         30
#define AQ_RS_SRC_ADDRESS_ADDRESS_Start                                        0

// Register AQRsSrcStride.
// ~~~~~~~~~~~~~~~~~~~~~~

// Source color stride.

#define AQRsSrcStrideRegAddrs                                             0x0583
#define AQ_RS_SRC_STRIDE_Address                                         0x0160C
#define AQ_RS_SRC_STRIDE_MSB                                                  15
#define AQ_RS_SRC_STRIDE_LSB                                                   0
#define AQ_RS_SRC_STRIDE_Count                                                 1
#define AQ_RS_SRC_STRIDE_FieldMask                                    0x0003FFFF
#define AQ_RS_SRC_STRIDE_ReadMask                                     0x0003FFFC
#define AQ_RS_SRC_STRIDE_WriteMask                                    0x0003FFFC
#define AQ_RS_SRC_STRIDE_ResetValue                                   0x00000000

#define AQ_RS_SRC_STRIDE_STRIDE                                             17:0
#define AQ_RS_SRC_STRIDE_STRIDE_End                                           17
#define AQ_RS_SRC_STRIDE_STRIDE_Start                                          0

// Register AQRsDestAddress.
// ~~~~~~~~~~~~~~~~~~~~~~~~

// Destination address.

#define AQRsDestAddressRegAddrs                                           0x0584
#define AQ_RS_DEST_ADDRESS_Address                                       0x01610
#define AQ_RS_DEST_ADDRESS_MSB                                                15
#define AQ_RS_DEST_ADDRESS_LSB                                                 0
#define AQ_RS_DEST_ADDRESS_Count                                               1
#define AQ_RS_DEST_ADDRESS_FieldMask                                  0xFFFFFFFF
#define AQ_RS_DEST_ADDRESS_ReadMask                                   0xFFFFFFFC
#define AQ_RS_DEST_ADDRESS_WriteMask                                  0xFFFFFFFC
#define AQ_RS_DEST_ADDRESS_ResetValue                                 0x00000000

#define AQ_RS_DEST_ADDRESS_TYPE                                            31:31
#define AQ_RS_DEST_ADDRESS_TYPE_End                                           31
#define AQ_RS_DEST_ADDRESS_TYPE_Start                                         31
#define   AQ_RS_DEST_ADDRESS_TYPE_SYSTEM                                     0x0
#define   AQ_RS_DEST_ADDRESS_TYPE_VIRTUAL_SYSTEM                             0x1

#define AQ_RS_DEST_ADDRESS_ADDRESS                                          30:0
#define AQ_RS_DEST_ADDRESS_ADDRESS_End                                        30
#define AQ_RS_DEST_ADDRESS_ADDRESS_Start                                       0

// Register AQRsDestStride.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Destination stride.

#define AQRsDestStrideRegAddrs                                            0x0585
#define AQ_RS_DEST_STRIDE_Address                                        0x01614
#define AQ_RS_DEST_STRIDE_MSB                                                 15
#define AQ_RS_DEST_STRIDE_LSB                                                  0
#define AQ_RS_DEST_STRIDE_Count                                                1
#define AQ_RS_DEST_STRIDE_FieldMask                                   0x0003FFFF
#define AQ_RS_DEST_STRIDE_ReadMask                                    0x0003FFFC
#define AQ_RS_DEST_STRIDE_WriteMask                                   0x0003FFFC
#define AQ_RS_DEST_STRIDE_ResetValue                                  0x00000000

#define AQ_RS_DEST_STRIDE_STRIDE                                            17:0
#define AQ_RS_DEST_STRIDE_STRIDE_End                                          17
#define AQ_RS_DEST_STRIDE_STRIDE_Start                                         0

// Register AQRsDepSrcAddress.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~

// Depth address.

#define AQRsDepSrcAddressRegAddrs                                         0x0586
#define AQ_RS_DEP_SRC_ADDRESS_Address                                    0x01618
#define AQ_RS_DEP_SRC_ADDRESS_MSB                                             15
#define AQ_RS_DEP_SRC_ADDRESS_LSB                                              0
#define AQ_RS_DEP_SRC_ADDRESS_Count                                            1
#define AQ_RS_DEP_SRC_ADDRESS_FieldMask                               0xFFFFFFFF
#define AQ_RS_DEP_SRC_ADDRESS_ReadMask                                0xFFFFFFFC
#define AQ_RS_DEP_SRC_ADDRESS_WriteMask                               0xFFFFFFFC
#define AQ_RS_DEP_SRC_ADDRESS_ResetValue                              0x00000000

#define AQ_RS_DEP_SRC_ADDRESS_TYPE                                         31:31
#define AQ_RS_DEP_SRC_ADDRESS_TYPE_End                                        31
#define AQ_RS_DEP_SRC_ADDRESS_TYPE_Start                                      31
#define   AQ_RS_DEP_SRC_ADDRESS_TYPE_SYSTEM                                  0x0
#define   AQ_RS_DEP_SRC_ADDRESS_TYPE_VIRTUAL_SYSTEM                          0x1

#define AQ_RS_DEP_SRC_ADDRESS_ADDRESS                                       30:0
#define AQ_RS_DEP_SRC_ADDRESS_ADDRESS_End                                     30
#define AQ_RS_DEP_SRC_ADDRESS_ADDRESS_Start                                    0

// Register AQRsDepSrcStride.
// ~~~~~~~~~~~~~~~~~~~~~~~~~

// Depth stride.

#define AQRsDepSrcStrideRegAddrs                                          0x0587
#define AQ_RS_DEP_SRC_STRIDE_Address                                     0x0161C
#define AQ_RS_DEP_SRC_STRIDE_MSB                                              15
#define AQ_RS_DEP_SRC_STRIDE_LSB                                               0
#define AQ_RS_DEP_SRC_STRIDE_Count                                             1
#define AQ_RS_DEP_SRC_STRIDE_FieldMask                                0x0003FFFF
#define AQ_RS_DEP_SRC_STRIDE_ReadMask                                 0x0003FFFC
#define AQ_RS_DEP_SRC_STRIDE_WriteMask                                0x0003FFFC
#define AQ_RS_DEP_SRC_STRIDE_ResetValue                               0x00000000

#define AQ_RS_DEP_SRC_STRIDE_STRIDE                                         17:0
#define AQ_RS_DEP_SRC_STRIDE_STRIDE_End                                       17
#define AQ_RS_DEP_SRC_STRIDE_STRIDE_Start                                      0

// Register AQRsWindowSize.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Size of multi-sample window into target buffer.

#define AQRsWindowSizeRegAddrs                                            0x0588
#define AQ_RS_WINDOW_SIZE_Address                                        0x01620
#define AQ_RS_WINDOW_SIZE_MSB                                                 15
#define AQ_RS_WINDOW_SIZE_LSB                                                  0
#define AQ_RS_WINDOW_SIZE_Count                                                1
#define AQ_RS_WINDOW_SIZE_FieldMask                                   0xFFFFFFFF
#define AQ_RS_WINDOW_SIZE_ReadMask                                    0xFFFFFFFF
#define AQ_RS_WINDOW_SIZE_WriteMask                                   0xFFFFFFFF
#define AQ_RS_WINDOW_SIZE_ResetValue                                  0x00000000

// 16-bit width of multi-sample window into target buffer.
#define AQ_RS_WINDOW_SIZE_WIDTH                                             15:0
#define AQ_RS_WINDOW_SIZE_WIDTH_End                                           15
#define AQ_RS_WINDOW_SIZE_WIDTH_Start                                          0

// 16-bit height of multi-sample window into target buffer.
#define AQ_RS_WINDOW_SIZE_HEIGHT                                           31:16
#define AQ_RS_WINDOW_SIZE_HEIGHT_End                                          31
#define AQ_RS_WINDOW_SIZE_HEIGHT_Start                                        16

// Register AQRsEdgeDetectThresh.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQRsEdgeDetectThreshRegAddrs                                      0x0589
#define AQ_RS_EDGE_DETECT_THRESH_Address                                 0x01624
#define AQ_RS_EDGE_DETECT_THRESH_MSB                                          15
#define AQ_RS_EDGE_DETECT_THRESH_LSB                                           0
#define AQ_RS_EDGE_DETECT_THRESH_Count                                         1
#define AQ_RS_EDGE_DETECT_THRESH_FieldMask                            0x00FFFFFF
#define AQ_RS_EDGE_DETECT_THRESH_ReadMask                             0x00FFFFFF
#define AQ_RS_EDGE_DETECT_THRESH_WriteMask                            0x00FFFFFF
#define AQ_RS_EDGE_DETECT_THRESH_ResetValue                           0x00000000

// Edge detect threshold (lower threshold, more filtering).
#define AQ_RS_EDGE_DETECT_THRESH_VALUE                                      23:0
#define AQ_RS_EDGE_DETECT_THRESH_VALUE_End                                    23
#define AQ_RS_EDGE_DETECT_THRESH_VALUE_Start                                   0

// Register AQRsEdgeFilterCoef.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~

// Filter coefficients.

#define AQRsEdgeFilterCoefRegAddrs                                        0x058A
#define AQ_RS_EDGE_FILTER_COEF_Address                                   0x01628
#define AQ_RS_EDGE_FILTER_COEF_MSB                                            15
#define AQ_RS_EDGE_FILTER_COEF_LSB                                             0
#define AQ_RS_EDGE_FILTER_COEF_Count                                           1
#define AQ_RS_EDGE_FILTER_COEF_FieldMask                              0x0003FFFF
#define AQ_RS_EDGE_FILTER_COEF_ReadMask                               0x0003FFFF
#define AQ_RS_EDGE_FILTER_COEF_WriteMask                              0x0003FFFF
#define AQ_RS_EDGE_FILTER_COEF_ResetValue                             0x00000000

#define AQ_RS_EDGE_FILTER_COEF_CORNERS                                       5:0
#define AQ_RS_EDGE_FILTER_COEF_CORNERS_End                                     5
#define AQ_RS_EDGE_FILTER_COEF_CORNERS_Start                                   0

#define AQ_RS_EDGE_FILTER_COEF_SIDES                                        11:6
#define AQ_RS_EDGE_FILTER_COEF_SIDES_End                                      11
#define AQ_RS_EDGE_FILTER_COEF_SIDES_Start                                     6

#define AQ_RS_EDGE_FILTER_COEF_CENTER                                      17:12
#define AQ_RS_EDGE_FILTER_COEF_CENTER_End                                     17
#define AQ_RS_EDGE_FILTER_COEF_CENTER_Start                                   12

// Register AQRsDitherTable (2 in total).
// ~~~~~~~~~~~~~~~~~~~~~~~~

// Dither table.

#define AQRsDitherTableRegAddrs                                           0x058C
#define AQ_RS_DITHER_TABLE_Address                                       0x01630
#define AQ_RS_DITHER_TABLE_MSB                                                15
#define AQ_RS_DITHER_TABLE_LSB                                                 1
#define AQ_RS_DITHER_TABLE_Count                                               2
#define AQ_RS_DITHER_TABLE_FieldMask                                  0xFFFFFFFF
#define AQ_RS_DITHER_TABLE_ReadMask                                   0xFFFFFFFF
#define AQ_RS_DITHER_TABLE_WriteMask                                  0xFFFFFFFF
#define AQ_RS_DITHER_TABLE_ResetValue                                 0x00000000

#define AQ_RS_DITHER_TABLE_B0                                                7:0
#define AQ_RS_DITHER_TABLE_B0_End                                              7
#define AQ_RS_DITHER_TABLE_B0_Start                                            0

#define AQ_RS_DITHER_TABLE_B1                                               15:8
#define AQ_RS_DITHER_TABLE_B1_End                                             15
#define AQ_RS_DITHER_TABLE_B1_Start                                            8

#define AQ_RS_DITHER_TABLE_B2                                              23:16
#define AQ_RS_DITHER_TABLE_B2_End                                             23
#define AQ_RS_DITHER_TABLE_B2_Start                                           16

#define AQ_RS_DITHER_TABLE_B3                                              31:24
#define AQ_RS_DITHER_TABLE_B3_End                                             31
#define AQ_RS_DITHER_TABLE_B3_Start                                           24

// Register AQRsNonFilterFrontZ.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQRsNonFilterFrontZRegAddrs                                       0x058B
#define AQ_RS_NON_FILTER_FRONT_Z_Address                                 0x0162C
#define AQ_RS_NON_FILTER_FRONT_Z_MSB                                          15
#define AQ_RS_NON_FILTER_FRONT_Z_LSB                                           0
#define AQ_RS_NON_FILTER_FRONT_Z_Count                                         1
#define AQ_RS_NON_FILTER_FRONT_Z_FieldMask                            0xFFFFFFFF
#define AQ_RS_NON_FILTER_FRONT_Z_ReadMask                             0xFFFFFFFF
#define AQ_RS_NON_FILTER_FRONT_Z_WriteMask                            0xFFFFFFFF
#define AQ_RS_NON_FILTER_FRONT_Z_ResetValue                           0x00000000

// Front filter depth value.
#define AQ_RS_NON_FILTER_FRONT_Z_RS_NON_FILTER_FRONT_Z                      31:0
#define AQ_RS_NON_FILTER_FRONT_Z_RS_NON_FILTER_FRONT_Z_End                    31
#define AQ_RS_NON_FILTER_FRONT_Z_RS_NON_FILTER_FRONT_Z_Start                   0

// Register AQRsDebug.
// ~~~~~~~~~~~~~~~~~~
#define AQRsDebugRegAddrs                                                 0x058E
#define AQ_RS_DEBUG_Address                                              0x01638
#define AQ_RS_DEBUG_MSB                                                       15
#define AQ_RS_DEBUG_LSB                                                        0
#define AQ_RS_DEBUG_Count                                                      1
#define AQ_RS_DEBUG_FieldMask                                         0x0000003F
#define AQ_RS_DEBUG_ReadMask                                          0x0000003F
#define AQ_RS_DEBUG_WriteMask                                         0x0000003F
#define AQ_RS_DEBUG_ResetValue                                        0x00000006

// To reduce memory bandwith during supersampling, reduce
// this value (should be greater than 3 and less than 12).
#define AQ_RS_DEBUG_FILTER_TILE_COUNT                                        5:0
#define AQ_RS_DEBUG_FILTER_TILE_COUNT_End                                      5
#define AQ_RS_DEBUG_FILTER_TILE_COUNT_Start                                    0

// Register AQRsClearValue (4 in total).
// ~~~~~~~~~~~~~~~~~~~~~~~
#define AQRsClearValueRegAddrs                                            0x0590
#define AQ_RS_CLEAR_VALUE_Address                                        0x01640
#define AQ_RS_CLEAR_VALUE_MSB                                                 15
#define AQ_RS_CLEAR_VALUE_LSB                                                  2
#define AQ_RS_CLEAR_VALUE_Count                                                4
#define AQ_RS_CLEAR_VALUE_FieldMask                                   0xFFFFFFFF
#define AQ_RS_CLEAR_VALUE_ReadMask                                    0xFFFFFFFF
#define AQ_RS_CLEAR_VALUE_WriteMask                                   0xFFFFFFFF
#define AQ_RS_CLEAR_VALUE_ResetValue                                  0x00000000

// Clear value for each of the 4 tiles.
#define AQ_RS_CLEAR_VALUE_VALUE                                             31:0
#define AQ_RS_CLEAR_VALUE_VALUE_End                                           31
#define AQ_RS_CLEAR_VALUE_VALUE_Start                                          0

// Register AQRsClearControl.
// ~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQRsClearControlRegAddrs                                          0x058F
#define AQ_RS_CLEAR_CONTROL_Address                                      0x0163C
#define AQ_RS_CLEAR_CONTROL_MSB                                               15
#define AQ_RS_CLEAR_CONTROL_LSB                                                0
#define AQ_RS_CLEAR_CONTROL_Count                                              1
#define AQ_RS_CLEAR_CONTROL_FieldMask                                 0x0003FFFF
#define AQ_RS_CLEAR_CONTROL_ReadMask                                  0x0003FFFF
#define AQ_RS_CLEAR_CONTROL_WriteMask                                 0x0003FFFF
#define AQ_RS_CLEAR_CONTROL_ResetValue                                0x00000000

// Enables clearing.
#define AQ_RS_CLEAR_CONTROL_ENABLE                                         17:16
#define AQ_RS_CLEAR_CONTROL_ENABLE_End                                        17
#define AQ_RS_CLEAR_CONTROL_ENABLE_Start                                      16
#define   AQ_RS_CLEAR_CONTROL_ENABLE_DISABLED                                0x0
#define   AQ_RS_CLEAR_CONTROL_ENABLE_CLEAR_ONE                               0x1
#define   AQ_RS_CLEAR_CONTROL_ENABLE_CLEAR_FOUR                              0x2

// Byte mask for each of the 32-bit clear values.
#define AQ_RS_CLEAR_CONTROL_MASK                                            15:0
#define AQ_RS_CLEAR_CONTROL_MASK_End                                          15
#define AQ_RS_CLEAR_CONTROL_MASK_Start                                         0

// Register gcTileCacheFlush.
// ~~~~~~~~~~~~~~~~~~~~~~~~~

// Flush the different caches inside the memory controller.

#define gcTileCacheFlushRegAddrs                                          0x0594
#define GC_TILE_CACHE_FLUSH_Address                                      0x01650
#define GC_TILE_CACHE_FLUSH_MSB                                               15
#define GC_TILE_CACHE_FLUSH_LSB                                                0
#define GC_TILE_CACHE_FLUSH_Count                                              1
#define GC_TILE_CACHE_FLUSH_FieldMask                                 0x00000071
#define GC_TILE_CACHE_FLUSH_ReadMask                                  0x00000071
#define GC_TILE_CACHE_FLUSH_WriteMask                                 0x00000071
#define GC_TILE_CACHE_FLUSH_ResetValue                                0x00000000

// Flush the tile cache.
#define GC_TILE_CACHE_FLUSH_FLUSH                                            0:0
#define GC_TILE_CACHE_FLUSH_FLUSH_End                                          0
#define GC_TILE_CACHE_FLUSH_FLUSH_Start                                        0
#define   GC_TILE_CACHE_FLUSH_FLUSH_DISABLE                                  0x0
#define   GC_TILE_CACHE_FLUSH_FLUSH_ENABLE                                   0x1

// Reset Z buffer auto-disable counter to zero.
#define GC_TILE_CACHE_FLUSH_RESET_ZCOUNTER                                   4:4
#define GC_TILE_CACHE_FLUSH_RESET_ZCOUNTER_End                                 4
#define GC_TILE_CACHE_FLUSH_RESET_ZCOUNTER_Start                               4
#define   GC_TILE_CACHE_FLUSH_RESET_ZCOUNTER_DISABLE                         0x0
#define   GC_TILE_CACHE_FLUSH_RESET_ZCOUNTER_ENABLE                          0x1

// Reset color buffer auto-disable counter to zero.
#define GC_TILE_CACHE_FLUSH_RESET_CCOUNTER                                   5:5
#define GC_TILE_CACHE_FLUSH_RESET_CCOUNTER_End                                 5
#define GC_TILE_CACHE_FLUSH_RESET_CCOUNTER_Start                               5
#define   GC_TILE_CACHE_FLUSH_RESET_CCOUNTER_DISABLE                         0x0
#define   GC_TILE_CACHE_FLUSH_RESET_CCOUNTER_ENABLE                          0x1

// Flush the 2nd level cache (if applicable).
#define GC_TILE_CACHE_FLUSH_FLUSH_L2                                         6:6
#define GC_TILE_CACHE_FLUSH_FLUSH_L2_End                                       6
#define GC_TILE_CACHE_FLUSH_FLUSH_L2_Start                                     6
#define   GC_TILE_CACHE_FLUSH_FLUSH_L2_DISABLE                               0x0
#define   GC_TILE_CACHE_FLUSH_FLUSH_L2_ENABLE                                0x1

// Register gcMemoryConfig.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Memory controller configuration register.
// Each tile has 4 bits to explain its status. 
// Below is the tile status register usage:
// 0: Normal
// 1: Cleared

#define gcMemoryConfigRegAddrs                                            0x0595
#define GC_MEMORY_CONFIG_Address                                         0x01654
#define GC_MEMORY_CONFIG_MSB                                                  15
#define GC_MEMORY_CONFIG_LSB                                                   0
#define GC_MEMORY_CONFIG_Count                                                 1
#define GC_MEMORY_CONFIG_FieldMask                                    0x33FF007F
#define GC_MEMORY_CONFIG_ReadMask                                     0x33FF007F
#define GC_MEMORY_CONFIG_WriteMask                                    0x33FF007F
#define GC_MEMORY_CONFIG_ResetValue                                   0x00200000

// Enable fast clear for depth.
#define GC_MEMORY_CONFIG_FAST_CLEAR_EN_Z                                     0:0
#define GC_MEMORY_CONFIG_FAST_CLEAR_EN_Z_End                                   0
#define GC_MEMORY_CONFIG_FAST_CLEAR_EN_Z_Start                                 0
#define   GC_MEMORY_CONFIG_FAST_CLEAR_EN_Z_DISABLE                           0x0
#define   GC_MEMORY_CONFIG_FAST_CLEAR_EN_Z_ENABLE                            0x1

// Enable fast clear for color.
#define GC_MEMORY_CONFIG_FAST_CLEAR_EN_C                                     1:1
#define GC_MEMORY_CONFIG_FAST_CLEAR_EN_C_End                                   1
#define GC_MEMORY_CONFIG_FAST_CLEAR_EN_C_Start                                 1
#define   GC_MEMORY_CONFIG_FAST_CLEAR_EN_C_DISABLE                           0x0
#define   GC_MEMORY_CONFIG_FAST_CLEAR_EN_C_ENABLE                            0x1

// Color is 16 bits.
#define GC_MEMORY_CONFIG_COLOR16_BIT                                         2:2
#define GC_MEMORY_CONFIG_COLOR16_BIT_End                                       2
#define GC_MEMORY_CONFIG_COLOR16_BIT_Start                                     2
#define   GC_MEMORY_CONFIG_COLOR16_BIT_DISABLE                               0x0
#define   GC_MEMORY_CONFIG_COLOR16_BIT_ENABLE                                0x1

// Depth is 16 bits.
#define GC_MEMORY_CONFIG_DEPTH16_BIT                                         3:3
#define GC_MEMORY_CONFIG_DEPTH16_BIT_End                                       3
#define GC_MEMORY_CONFIG_DEPTH16_BIT_Start                                     3
#define   GC_MEMORY_CONFIG_DEPTH16_BIT_DISABLE                               0x0
#define   GC_MEMORY_CONFIG_DEPTH16_BIT_ENABLE                                0x1

// Enable auto-disabling of fast clear for Z.
#define GC_MEMORY_CONFIG_AUTO_DISABLE_Z                                      4:4
#define GC_MEMORY_CONFIG_AUTO_DISABLE_Z_End                                    4
#define GC_MEMORY_CONFIG_AUTO_DISABLE_Z_Start                                  4
#define   GC_MEMORY_CONFIG_AUTO_DISABLE_Z_DISABLE                            0x0
#define   GC_MEMORY_CONFIG_AUTO_DISABLE_Z_ENABLE                             0x1

// Enable auto-disabling of fast clear for Color.
#define GC_MEMORY_CONFIG_AUTO_DISABLE_C                                      5:5
#define GC_MEMORY_CONFIG_AUTO_DISABLE_C_End                                    5
#define GC_MEMORY_CONFIG_AUTO_DISABLE_C_Start                                  5
#define   GC_MEMORY_CONFIG_AUTO_DISABLE_C_DISABLE                            0x0
#define   GC_MEMORY_CONFIG_AUTO_DISABLE_C_ENABLE                             0x1

// Enable compression.
#define GC_MEMORY_CONFIG_COMPRESSION_EN_Z                                    6:6
#define GC_MEMORY_CONFIG_COMPRESSION_EN_Z_End                                  6
#define GC_MEMORY_CONFIG_COMPRESSION_EN_Z_Start                                6
#define   GC_MEMORY_CONFIG_COMPRESSION_EN_Z_DISABLE                          0x0
#define   GC_MEMORY_CONFIG_COMPRESSION_EN_Z_ENABLE                           0x1

// Maximum number of prefetch requests in L2 cache (if applicable).
#define GC_MEMORY_CONFIG_MAX_PREFETCH_COUNT                                25:16
#define GC_MEMORY_CONFIG_MAX_PREFETCH_COUNT_End                               25
#define GC_MEMORY_CONFIG_MAX_PREFETCH_COUNT_Start                             16

// Disables L2 (if applicable).
#define GC_MEMORY_CONFIG_DISABLE_L2                                        28:28
#define GC_MEMORY_CONFIG_DISABLE_L2_End                                       28
#define GC_MEMORY_CONFIG_DISABLE_L2_Start                                     28

// In case the memory manager does not handle the issue of RAW, 
// fix it internally.
#define GC_MEMORY_CONFIG_FIX_RAW_HAZARDS                                   29:29
#define GC_MEMORY_CONFIG_FIX_RAW_HAZARDS_End                                  29
#define GC_MEMORY_CONFIG_FIX_RAW_HAZARDS_Start                                29

// Register gcColorCache.
// ~~~~~~~~~~~~~~~~~~~~~

// Base address for color tile cache.

#define gcColorCacheRegAddrs                                              0x0596
#define GC_COLOR_CACHE_Address                                           0x01658
#define GC_COLOR_CACHE_MSB                                                    15
#define GC_COLOR_CACHE_LSB                                                     0
#define GC_COLOR_CACHE_Count                                                   1
#define GC_COLOR_CACHE_FieldMask                                      0xFFFFFFFF
#define GC_COLOR_CACHE_ReadMask                                       0xFFFFFFFC
#define GC_COLOR_CACHE_WriteMask                                      0xFFFFFFFC
#define GC_COLOR_CACHE_ResetValue                                     0x00000000

#define GC_COLOR_CACHE_TYPE                                                31:31
#define GC_COLOR_CACHE_TYPE_End                                               31
#define GC_COLOR_CACHE_TYPE_Start                                             31
#define   GC_COLOR_CACHE_TYPE_SYSTEM                                         0x0
#define   GC_COLOR_CACHE_TYPE_VIRTUAL_SYSTEM                                 0x1

#define GC_COLOR_CACHE_ADDRESS                                              30:0
#define GC_COLOR_CACHE_ADDRESS_End                                            30
#define GC_COLOR_CACHE_ADDRESS_Start                                           0

// Register gcColorBase.
// ~~~~~~~~~~~~~~~~~~~~

// Base address for color buffer.

#define gcColorBaseRegAddrs                                               0x0597
#define GC_COLOR_BASE_Address                                            0x0165C
#define GC_COLOR_BASE_MSB                                                     15
#define GC_COLOR_BASE_LSB                                                      0
#define GC_COLOR_BASE_Count                                                    1
#define GC_COLOR_BASE_FieldMask                                       0xFFFFFFFF
#define GC_COLOR_BASE_ReadMask                                        0xFFFFFFFC
#define GC_COLOR_BASE_WriteMask                                       0xFFFFFFFC
#define GC_COLOR_BASE_ResetValue                                      0x00000000

#define GC_COLOR_BASE_TYPE                                                 31:31
#define GC_COLOR_BASE_TYPE_End                                                31
#define GC_COLOR_BASE_TYPE_Start                                              31
#define   GC_COLOR_BASE_TYPE_SYSTEM                                          0x0
#define   GC_COLOR_BASE_TYPE_VIRTUAL_SYSTEM                                  0x1

#define GC_COLOR_BASE_ADDRESS                                               30:0
#define GC_COLOR_BASE_ADDRESS_End                                             30
#define GC_COLOR_BASE_ADDRESS_Start                                            0

// Register gcColorClearValue.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~

// Value for cleared color buffer tiles.

#define gcColorClearValueRegAddrs                                         0x0598
#define GC_COLOR_CLEAR_VALUE_Address                                     0x01660
#define GC_COLOR_CLEAR_VALUE_MSB                                              15
#define GC_COLOR_CLEAR_VALUE_LSB                                               0
#define GC_COLOR_CLEAR_VALUE_Count                                             1
#define GC_COLOR_CLEAR_VALUE_FieldMask                                0xFFFFFFFF
#define GC_COLOR_CLEAR_VALUE_ReadMask                                 0xFFFFFFFF
#define GC_COLOR_CLEAR_VALUE_WriteMask                                0xFFFFFFFF
#define GC_COLOR_CLEAR_VALUE_ResetValue                               0x00000000

#define GC_COLOR_CLEAR_VALUE_VALUE                                          31:0
#define GC_COLOR_CLEAR_VALUE_VALUE_End                                        31
#define GC_COLOR_CLEAR_VALUE_VALUE_Start                                       0

// Register gcDepthCache.
// ~~~~~~~~~~~~~~~~~~~~~

// Base address for depth tile cache.

#define gcDepthCacheRegAddrs                                              0x0599
#define GC_DEPTH_CACHE_Address                                           0x01664
#define GC_DEPTH_CACHE_MSB                                                    15
#define GC_DEPTH_CACHE_LSB                                                     0
#define GC_DEPTH_CACHE_Count                                                   1
#define GC_DEPTH_CACHE_FieldMask                                      0xFFFFFFFF
#define GC_DEPTH_CACHE_ReadMask                                       0xFFFFFFFC
#define GC_DEPTH_CACHE_WriteMask                                      0xFFFFFFFC
#define GC_DEPTH_CACHE_ResetValue                                     0x00000000

#define GC_DEPTH_CACHE_TYPE                                                31:31
#define GC_DEPTH_CACHE_TYPE_End                                               31
#define GC_DEPTH_CACHE_TYPE_Start                                             31
#define   GC_DEPTH_CACHE_TYPE_SYSTEM                                         0x0
#define   GC_DEPTH_CACHE_TYPE_VIRTUAL_SYSTEM                                 0x1

#define GC_DEPTH_CACHE_ADDRESS                                              30:0
#define GC_DEPTH_CACHE_ADDRESS_End                                            30
#define GC_DEPTH_CACHE_ADDRESS_Start                                           0

// Register gcDepthBase.
// ~~~~~~~~~~~~~~~~~~~~

// Base address for depth buffer.

#define gcDepthBaseRegAddrs                                               0x059A
#define GC_DEPTH_BASE_Address                                            0x01668
#define GC_DEPTH_BASE_MSB                                                     15
#define GC_DEPTH_BASE_LSB                                                      0
#define GC_DEPTH_BASE_Count                                                    1
#define GC_DEPTH_BASE_FieldMask                                       0xFFFFFFFF
#define GC_DEPTH_BASE_ReadMask                                        0xFFFFFFFC
#define GC_DEPTH_BASE_WriteMask                                       0xFFFFFFFC
#define GC_DEPTH_BASE_ResetValue                                      0x00000000

#define GC_DEPTH_BASE_TYPE                                                 31:31
#define GC_DEPTH_BASE_TYPE_End                                                31
#define GC_DEPTH_BASE_TYPE_Start                                              31
#define   GC_DEPTH_BASE_TYPE_SYSTEM                                          0x0
#define   GC_DEPTH_BASE_TYPE_VIRTUAL_SYSTEM                                  0x1

#define GC_DEPTH_BASE_ADDRESS                                               30:0
#define GC_DEPTH_BASE_ADDRESS_End                                             30
#define GC_DEPTH_BASE_ADDRESS_Start                                            0

// Register gcDepthClearValue.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~

// Value for cleared depth buffer tiles.

#define gcDepthClearValueRegAddrs                                         0x059B
#define GC_DEPTH_CLEAR_VALUE_Address                                     0x0166C
#define GC_DEPTH_CLEAR_VALUE_MSB                                              15
#define GC_DEPTH_CLEAR_VALUE_LSB                                               0
#define GC_DEPTH_CLEAR_VALUE_Count                                             1
#define GC_DEPTH_CLEAR_VALUE_FieldMask                                0xFFFFFFFF
#define GC_DEPTH_CLEAR_VALUE_ReadMask                                 0xFFFFFFFF
#define GC_DEPTH_CLEAR_VALUE_WriteMask                                0xFFFFFFFF
#define GC_DEPTH_CLEAR_VALUE_ResetValue                               0x00000000

#define GC_DEPTH_CLEAR_VALUE_VALUE                                          31:0
#define GC_DEPTH_CLEAR_VALUE_VALUE_End                                        31
#define GC_DEPTH_CLEAR_VALUE_VALUE_Start                                       0

// Register gcTileStatusCounterZ.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

// Once the hardware has changed this number of tiles from 'cleared'
// to 'normal' it will automatically disable fast clear for Z buffers.
// Write to this register to reset the counters for new Z buffers.

#define gcTileStatusCounterZRegAddrs                                      0x059C
#define GC_TILE_STATUS_COUNTER_Z_Address                                 0x01670
#define GC_TILE_STATUS_COUNTER_Z_MSB                                          15
#define GC_TILE_STATUS_COUNTER_Z_LSB                                           0
#define GC_TILE_STATUS_COUNTER_Z_Count                                         1
#define GC_TILE_STATUS_COUNTER_Z_FieldMask                            0x000FFFFF
#define GC_TILE_STATUS_COUNTER_Z_ReadMask                             0x000FFFFF
#define GC_TILE_STATUS_COUNTER_Z_WriteMask                            0x000FFFFF
#define GC_TILE_STATUS_COUNTER_Z_ResetValue                           0x00000000

#define GC_TILE_STATUS_COUNTER_Z_COUNTER                                    19:0
#define GC_TILE_STATUS_COUNTER_Z_COUNTER_End                                  19
#define GC_TILE_STATUS_COUNTER_Z_COUNTER_Start                                 0

// Register gcTileStatusCounterC.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

// Once the hardware has changed this number of tiles from 'cleared'
// to 'normal' it will automatically disable fast clear for color buffers.
// Write to this register to reset the counters for new Color buffers.

#define gcTileStatusCounterCRegAddrs                                      0x059D
#define GC_TILE_STATUS_COUNTER_C_Address                                 0x01674
#define GC_TILE_STATUS_COUNTER_C_MSB                                          15
#define GC_TILE_STATUS_COUNTER_C_LSB                                           0
#define GC_TILE_STATUS_COUNTER_C_Count                                         1
#define GC_TILE_STATUS_COUNTER_C_FieldMask                            0x000FFFFF
#define GC_TILE_STATUS_COUNTER_C_ReadMask                             0x000FFFFF
#define GC_TILE_STATUS_COUNTER_C_WriteMask                            0x000FFFFF
#define GC_TILE_STATUS_COUNTER_C_ResetValue                           0x00000000

#define GC_TILE_STATUS_COUNTER_C_COUNTER                                    19:0
#define GC_TILE_STATUS_COUNTER_C_COUNTER_End                                  19
#define GC_TILE_STATUS_COUNTER_C_COUNTER_Start                                 0

// Register gcYUVTilerConfig.
// ~~~~~~~~~~~~~~~~~~~~~~~~~

// Configuration register for 4:2:0 tiler.

#define gcYUVTilerConfigRegAddrs                                          0x059E
#define GC_YUV_TILER_CONFIG_Address                                      0x01678
#define GC_YUV_TILER_CONFIG_MSB                                               15
#define GC_YUV_TILER_CONFIG_LSB                                                0
#define GC_YUV_TILER_CONFIG_Count                                              1
#define GC_YUV_TILER_CONFIG_FieldMask                                 0x00000011
#define GC_YUV_TILER_CONFIG_ReadMask                                  0x00000011
#define GC_YUV_TILER_CONFIG_WriteMask                                 0x00000011
#define GC_YUV_TILER_CONFIG_ResetValue                                0x00000000

// tile a 4:2:0 source image into a YUY2 4:2:2 target.
#define GC_YUV_TILER_CONFIG_TILER                                            0:0
#define GC_YUV_TILER_CONFIG_TILER_End                                          0
#define GC_YUV_TILER_CONFIG_TILER_Start                                        0
#define   GC_YUV_TILER_CONFIG_TILER_DISABLED                                 0x0
// Enables a special pass in resolve block to gather and
#define   GC_YUV_TILER_CONFIG_TILER_ENABLED                                  0x1

#define GC_YUV_TILER_CONFIG_FORMAT                                           4:4
#define GC_YUV_TILER_CONFIG_FORMAT_End                                         4
#define GC_YUV_TILER_CONFIG_FORMAT_Start                                       4
#define   GC_YUV_TILER_CONFIG_FORMAT_YV12                                    0x0
#define   GC_YUV_TILER_CONFIG_FORMAT_NV12                                    0x1

// Register gcYUVTilerSize.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Size of the area to convert in pixels.

#define gcYUVTilerSizeRegAddrs                                            0x059F
#define GC_YUV_TILER_SIZE_Address                                        0x0167C
#define GC_YUV_TILER_SIZE_MSB                                                 15
#define GC_YUV_TILER_SIZE_LSB                                                  0
#define GC_YUV_TILER_SIZE_Count                                                1
#define GC_YUV_TILER_SIZE_FieldMask                                   0xFFFFFFFF
#define GC_YUV_TILER_SIZE_ReadMask                                    0xFFFFFFFF
#define GC_YUV_TILER_SIZE_WriteMask                                   0xFFFFFFFF
#define GC_YUV_TILER_SIZE_ResetValue                                  0x00000000

#define GC_YUV_TILER_SIZE_WIDTH                                             15:0
#define GC_YUV_TILER_SIZE_WIDTH_End                                           15
#define GC_YUV_TILER_SIZE_WIDTH_Start                                          0

#define GC_YUV_TILER_SIZE_HEIGHT                                           31:16
#define GC_YUV_TILER_SIZE_HEIGHT_End                                          31
#define GC_YUV_TILER_SIZE_HEIGHT_Start                                        16

// Register gcYUVTilerYbase.
// ~~~~~~~~~~~~~~~~~~~~~~~~

// Y plane base address.

#define gcYUVTilerYbaseRegAddrs                                           0x05A0
#define GC_YUV_TILER_YBASE_Address                                       0x01680
#define GC_YUV_TILER_YBASE_MSB                                                15
#define GC_YUV_TILER_YBASE_LSB                                                 0
#define GC_YUV_TILER_YBASE_Count                                               1
#define GC_YUV_TILER_YBASE_FieldMask                                  0xFFFFFFFF
#define GC_YUV_TILER_YBASE_ReadMask                                   0xFFFFFFFC
#define GC_YUV_TILER_YBASE_WriteMask                                  0xFFFFFFFC
#define GC_YUV_TILER_YBASE_ResetValue                                 0x00000000

#define GC_YUV_TILER_YBASE_TYPE                                            31:31
#define GC_YUV_TILER_YBASE_TYPE_End                                           31
#define GC_YUV_TILER_YBASE_TYPE_Start                                         31
#define   GC_YUV_TILER_YBASE_TYPE_SYSTEM                                     0x0
#define   GC_YUV_TILER_YBASE_TYPE_VIRTUAL_SYSTEM                             0x1

#define GC_YUV_TILER_YBASE_ADDRESS                                          30:0
#define GC_YUV_TILER_YBASE_ADDRESS_End                                        30
#define GC_YUV_TILER_YBASE_ADDRESS_Start                                       0

// Register gcYUVTilerYstride.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~

// Y plane stride.

#define gcYUVTilerYstrideRegAddrs                                         0x05A1
#define GC_YUV_TILER_YSTRIDE_Address                                     0x01684
#define GC_YUV_TILER_YSTRIDE_MSB                                              15
#define GC_YUV_TILER_YSTRIDE_LSB                                               0
#define GC_YUV_TILER_YSTRIDE_Count                                             1
#define GC_YUV_TILER_YSTRIDE_FieldMask                                0x0003FFFF
#define GC_YUV_TILER_YSTRIDE_ReadMask                                 0x0003FFFC
#define GC_YUV_TILER_YSTRIDE_WriteMask                                0x0003FFFC
#define GC_YUV_TILER_YSTRIDE_ResetValue                               0x00000000

#define GC_YUV_TILER_YSTRIDE_STRIDE                                         17:0
#define GC_YUV_TILER_YSTRIDE_STRIDE_End                                       17
#define GC_YUV_TILER_YSTRIDE_STRIDE_Start                                      0

// Register gcYUVTilerUbase.
// ~~~~~~~~~~~~~~~~~~~~~~~~

// U plane base address.

#define gcYUVTilerUbaseRegAddrs                                           0x05A2
#define GC_YUV_TILER_UBASE_Address                                       0x01688
#define GC_YUV_TILER_UBASE_MSB                                                15
#define GC_YUV_TILER_UBASE_LSB                                                 0
#define GC_YUV_TILER_UBASE_Count                                               1
#define GC_YUV_TILER_UBASE_FieldMask                                  0xFFFFFFFF
#define GC_YUV_TILER_UBASE_ReadMask                                   0xFFFFFFFC
#define GC_YUV_TILER_UBASE_WriteMask                                  0xFFFFFFFC
#define GC_YUV_TILER_UBASE_ResetValue                                 0x00000000

#define GC_YUV_TILER_UBASE_TYPE                                            31:31
#define GC_YUV_TILER_UBASE_TYPE_End                                           31
#define GC_YUV_TILER_UBASE_TYPE_Start                                         31
#define   GC_YUV_TILER_UBASE_TYPE_SYSTEM                                     0x0
#define   GC_YUV_TILER_UBASE_TYPE_VIRTUAL_SYSTEM                             0x1

#define GC_YUV_TILER_UBASE_ADDRESS                                          30:0
#define GC_YUV_TILER_UBASE_ADDRESS_End                                        30
#define GC_YUV_TILER_UBASE_ADDRESS_Start                                       0

// Register gcYUVTilerUstride.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~

// U plane stride.

#define gcYUVTilerUstrideRegAddrs                                         0x05A3
#define GC_YUV_TILER_USTRIDE_Address                                     0x0168C
#define GC_YUV_TILER_USTRIDE_MSB                                              15
#define GC_YUV_TILER_USTRIDE_LSB                                               0
#define GC_YUV_TILER_USTRIDE_Count                                             1
#define GC_YUV_TILER_USTRIDE_FieldMask                                0x0003FFFF
#define GC_YUV_TILER_USTRIDE_ReadMask                                 0x0003FFFC
#define GC_YUV_TILER_USTRIDE_WriteMask                                0x0003FFFC
#define GC_YUV_TILER_USTRIDE_ResetValue                               0x00000000

#define GC_YUV_TILER_USTRIDE_STRIDE                                         17:0
#define GC_YUV_TILER_USTRIDE_STRIDE_End                                       17
#define GC_YUV_TILER_USTRIDE_STRIDE_Start                                      0

// Register gcYUVTilerVbase.
// ~~~~~~~~~~~~~~~~~~~~~~~~

// V plane base address.

#define gcYUVTilerVbaseRegAddrs                                           0x05A4
#define GC_YUV_TILER_VBASE_Address                                       0x01690
#define GC_YUV_TILER_VBASE_MSB                                                15
#define GC_YUV_TILER_VBASE_LSB                                                 0
#define GC_YUV_TILER_VBASE_Count                                               1
#define GC_YUV_TILER_VBASE_FieldMask                                  0xFFFFFFFF
#define GC_YUV_TILER_VBASE_ReadMask                                   0xFFFFFFFC
#define GC_YUV_TILER_VBASE_WriteMask                                  0xFFFFFFFC
#define GC_YUV_TILER_VBASE_ResetValue                                 0x00000000

#define GC_YUV_TILER_VBASE_TYPE                                            31:31
#define GC_YUV_TILER_VBASE_TYPE_End                                           31
#define GC_YUV_TILER_VBASE_TYPE_Start                                         31
#define   GC_YUV_TILER_VBASE_TYPE_SYSTEM                                     0x0
#define   GC_YUV_TILER_VBASE_TYPE_VIRTUAL_SYSTEM                             0x1

#define GC_YUV_TILER_VBASE_ADDRESS                                          30:0
#define GC_YUV_TILER_VBASE_ADDRESS_End                                        30
#define GC_YUV_TILER_VBASE_ADDRESS_Start                                       0

// Register gcYUVTilerVstride.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~

// V plane stride.

#define gcYUVTilerVstrideRegAddrs                                         0x05A5
#define GC_YUV_TILER_VSTRIDE_Address                                     0x01694
#define GC_YUV_TILER_VSTRIDE_MSB                                              15
#define GC_YUV_TILER_VSTRIDE_LSB                                               0
#define GC_YUV_TILER_VSTRIDE_Count                                             1
#define GC_YUV_TILER_VSTRIDE_FieldMask                                0x0003FFFF
#define GC_YUV_TILER_VSTRIDE_ReadMask                                 0x0003FFFC
#define GC_YUV_TILER_VSTRIDE_WriteMask                                0x0003FFFC
#define GC_YUV_TILER_VSTRIDE_ResetValue                               0x00000000

#define GC_YUV_TILER_VSTRIDE_STRIDE                                         17:0
#define GC_YUV_TILER_VSTRIDE_STRIDE_End                                       17
#define GC_YUV_TILER_VSTRIDE_STRIDE_Start                                      0

// Register gcYUVTilerDestBase.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~

// Tiled destination base address.

#define gcYUVTilerDestBaseRegAddrs                                        0x05A6
#define GC_YUV_TILER_DEST_BASE_Address                                   0x01698
#define GC_YUV_TILER_DEST_BASE_MSB                                            15
#define GC_YUV_TILER_DEST_BASE_LSB                                             0
#define GC_YUV_TILER_DEST_BASE_Count                                           1
#define GC_YUV_TILER_DEST_BASE_FieldMask                              0xFFFFFFFF
#define GC_YUV_TILER_DEST_BASE_ReadMask                               0xFFFFFFFC
#define GC_YUV_TILER_DEST_BASE_WriteMask                              0xFFFFFFFC
#define GC_YUV_TILER_DEST_BASE_ResetValue                             0x00000000

#define GC_YUV_TILER_DEST_BASE_TYPE                                        31:31
#define GC_YUV_TILER_DEST_BASE_TYPE_End                                       31
#define GC_YUV_TILER_DEST_BASE_TYPE_Start                                     31
#define   GC_YUV_TILER_DEST_BASE_TYPE_SYSTEM                                 0x0
#define   GC_YUV_TILER_DEST_BASE_TYPE_VIRTUAL_SYSTEM                         0x1

#define GC_YUV_TILER_DEST_BASE_ADDRESS                                      30:0
#define GC_YUV_TILER_DEST_BASE_ADDRESS_End                                    30
#define GC_YUV_TILER_DEST_BASE_ADDRESS_Start                                   0

// Register gcYUVTilerDestStride.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

// Tiled destination stride.

#define gcYUVTilerDestStrideRegAddrs                                      0x05A7
#define GC_YUV_TILER_DEST_STRIDE_Address                                 0x0169C
#define GC_YUV_TILER_DEST_STRIDE_MSB                                          15
#define GC_YUV_TILER_DEST_STRIDE_LSB                                           0
#define GC_YUV_TILER_DEST_STRIDE_Count                                         1
#define GC_YUV_TILER_DEST_STRIDE_FieldMask                            0x0003FFFF
#define GC_YUV_TILER_DEST_STRIDE_ReadMask                             0x0003FFFC
#define GC_YUV_TILER_DEST_STRIDE_WriteMask                            0x0003FFFC
#define GC_YUV_TILER_DEST_STRIDE_ResetValue                           0x00000000

#define GC_YUV_TILER_DEST_STRIDE_STRIDE                                     17:0
#define GC_YUV_TILER_DEST_STRIDE_STRIDE_End                                   17
#define GC_YUV_TILER_DEST_STRIDE_STRIDE_Start                                  0

